1. Cross-Reference to Related Applications
The present invention is related to subject matter disclosed in, U.S. patent application entitled, “Method And System For Generating and Utilizing Speculative Memory Access Requests in Data Processing Systems”, application Ser. No. 09/208,569, naming Geoffrey S. S. Strongin and Qadeer A. Qureshi as inventors and filed Dec. 9, 1998; and to U.S. patent application entitled, “Method and Apparatus for Page-State Sensitive Memory Control and Access in Data Processing Systems”, application Ser. No. 09/207,971, naming Geoffrey S. S. Strongin and Qadeer A. Qureshi as inventors and filed Dec. 9, 1998, which applications are incorporated herein by reference.
2. Field of the Invention
The present invention relates generally to computer systems and more particularly to memory control functions within computer systems.
3. Description of the Related Art
In conventional computer systems, such as personal computer systems utilizing x86 based processors, the processor, along with other components in the computer system, are coupled to main system memory through an integrated circuit known in the art as the “North Bridge.” The North Bridge provides a memory control function as well as a bridge function between the host bus connected the processor and system input/output buses such as the Peripheral Component Interconnect (PCI) bus and the devices connected to the PCI bus.
In current architectures, the PCI bus provides the major I/O bus for the computer system. Other buses are commonly found in conventional computer systems. One such bus is the Universal Serial Bus (USB) bus and another bus is the IEEE 1394 bus. USB and 1394 traffic typically communicate with system memory through a South Bridge integrated circuit, which is coupled to the PCI bus. The South Bridge provides a bridge function between the PCI bus and other buses. In addition, the South Bridge provides for such functions as communication with a variety of legacy devices and provides power management functions. In any case, the buses at issue, and the devices which couple to those buses access system memory through the PCI bus.
One exception is a graphics bus, the Accelerated Graphics Port (AGP), which has been developed to both (1) reduce the load on the PCI bus systems, and (2) extend the graphics capabilities of systems. The AGP interface standard (defined by Accelerated Graphics Port Interface Specification, Revision 1.0 (31 Jul. 1996) from Intel corporation), allows the graphics processor to retrieve graphics information from system memory independently of the PCI.
In current industry architectures, the host bus, the AGP interconnect, and the PCI bus access system memory through the memory controller in the North Bridge. The memory controller maps logical addresses used by the processor to physical locations in system memory. The system memory controlled by the North Bridge is typically made up of a plurality of Direct Random Access Memory chips (DRAMs). There are a number of different types of DRAMs that may be used in system memory in current and future memory systems, such as RDRAM (Rambus DRAM), SDRAM (Synchronous DRAM), DDRSDRAM (Double data rate SDRAM).
DRAMs are organized into various banks. Each bank is comprised of a matrix of storage locations organized in rows and columns. When a memory access occurs, such as a read cycle, the memory controller receives an address over one of the buses, maps the received address into an appropriate physical address and performs the access operation to system memory. Consequently, an address, which for sake of illustration will be assumed to be 16 bits long, customarily is conceived of as being composed of two parts: a first 8-bit portion of the address which is associated with a row address, and a second 8-bit portion which is associated with a column address (the bit lengths are exemplary and merely utilized here for illustrative purposes). This separation of the address into row and column portions allows the address to correctly specify a storage location, or cell, by its row and column.
In order to minimize the number of pins on the DRAM, memory accesses in conventional DRAMs typically place the row portion of the address on the address bus to select the appropriate row, and then place the column portion of the address on the address bus to select the appropriate column. At some time after the row and column information have both been specified, the data from the memory location specified by the row and column address appears on the DRAM data bus.
From the foregoing, it can be seen that in order to make a single memory access there are three phases: a row address phase, a column address phase, and a data retrieval phase. In the past, it was noticed that typical programs tend to operate sequentially, so if there is a memory address accessed, it is likely that the next memory address accessed will be the very next cell, which means that the column address is likely to change, while the row address is not likely to change. Consequently, typical DRAMs are structured such that once the row address has been provided, thereafter DRAMS can continue to access the row (also referred to herein as page) that is “open” in the DRAM.
In the event that a memory controller has several memory accesses to be done sequentially, then once a page is open it would be desirable from an efficiency standpoint to examine pending as well as current memory accesses in order to determine which of those pending memory accesses will be to memory locations that are within a currently open page (that is, the row of the request is the row from which a memory controller is currently reading within a DRAM). In other words, assuming a page X is open, if there are four memory accesses A, B, C, and D, waiting to be performed, and assuming the first access A is to page Z, the second access B is to page X, the third access C is to page Y, and the fourth access D is to page W, it is preferable from a memory efficiency standpoint that the data access (i.e., access B) to the page that is open (i.e., page X) be made first.
Current memory controllers do not typically “look ahead” to see if certain pending memory accesses are destined for currently open pages based on the type of stream that is currently accessing memory. Furthermore, at any given time, typically more than one page of memory is generally open and in future systems this will become more likely. For example, under the Direct RDRAM scheme, it is expected that up to 8 pages per RDRAM chip will be open simultaneously. Thus, if a system has eight RDRAM chips (a reasonable assumption), it will be possible to have up to 64 pages open simultaneously.
Controlling memory access via the use of “look ahead” would be undeniably valuable. Furthermore, as the foregoing has shown, the prospective ability of the memory controllers to schedule memory access on the basis of look ahead is likely to become even more important in that future system memories are likely to be able to provide a very large number of open pages of memory simultaneously. It is therefore apparent that a need exists in the art for a method and system which will provide data processing systems, having memory controllers, with the ability to look ahead and intelligently schedule accesses to system memory utilizing information gained from such looking ahead.
In addition to the foregoing, another problem of concern to memory designers and memory controller designers is the issue of power consumption by the memory devices. Advanced DRAMs achieve higher performance but pay a penalty in higher power consumption. The more pages that are open, the more power is consumed. To address power concerns, some DRAMs provide reduced power modes in which some or all of a given memory component can be placed in a reduced power mode. However, such reduced power modes are provided at the cost of significantly increased latency. It would be desirable to be able to control memory to reduce power consumption without an associated large increase in latency by intelligently using the information available about current and pending transactions.